As IC (Integrated Circuit) geometries have become smaller, crosstalk has increasingly caused problems in IC design. Crosstalk occurs when two signals become partially superimposed on each other due to electromagnetic (inductive) or electrostatic (capacitive) coupling between the conductors carrying those signals. Crosstalk may arise, for example, if a magnetic field caused by changing current flow in one wire induces a current in another, parallel wire. Crosstalk typically involves an aggressor wire inducing timing changes and/or noise on a victim wire. Crosstalk often increases or decreases the delays within a circuit, and these varied delays can in turn lead to timing violations.
The timing analysis that identifies timing violations due to crosstalk is often performed by a sign-off EDA (Electronic Design Automation) tool. Typically, the sign-off tool is used to perform the final verification of an IC design (e.g., based on the design's performance, as determined by the sign-off tool, the design is “signed-off” for implementation in silicon). Since this timing analysis is performed as one of the final design stages, timing violations due to crosstalk are often not detected until relatively late in the design process.
Once timing violations due to crosstalk are detected, conventional processes for eliminating these timing violations may take several design iterations to implement. For example, one technique commonly used to reduce crosstalk effects between a pair of wires involves increasing the driver strength of the driver on the victim wire. However, this may in turn cause the wire that was previously a crosstalk victim to become a crosstalk aggressor with respect to another of its neighboring wires. As a result, another round of adjustments will be needed to deal with the new crosstalk effects, and adjustments made during that round are likely to cause additional crosstalk problems. Multiple design passes can be required to eliminate all of the timing violations.
As the above example shows, dealing with crosstalk effects can significantly complicate the final stages of the IC design process by adding several additional design iterations. These additional design iterations are undesirably expensive in terms of both time and resources needed to obtain an IC design that will pass sign-off timing analysis.